VIDEO PODCAST
SiFive's Krste Asanovic: New RISC-V Designs and AI Innovation
James Maguire
September 8, 2025

In this TechVoices conversation, Krste Asanovic, Co-Founder and Chief Architect at SiFive, outlines the company’s newest AI-focused RISC-V designs, including ultra-small X160 and X180 cores for pairing with custom accelerators, a new scalar co-processor interface (SSCI), deeper memory-latency tolerance, and specialized instructions for modern activation functions.

Asanovic contrasts SiFive’s IP-licensing model with proprietary approaches, details how open standards reduce fragmentation, and highlights real-world deployments of SiFive IP for processor cores—from electric vehicle ADAS to NASA’s spaceflight computers—while forecasting a continued shift toward general-purpose architectures.

Core Takeaways
Second-gen Intelligence launch
SiFive's new release builds on 40+ first-gen design wins and introduces ultra-compact X160 and X180 cores to sit beside customer accelerators—especially for power-sensitive edge AI.
New SSCI + memory advances
A scalar co-processor interface (alongside the existing vector interface), more efficient multi-core memory hierarchies, deeper latency tolerance, and new instructions target today's AI workloads.
Open RISC-V reduces fragmentation
Profiles such as RVA23 standardize the software target while letting vendors tailor extensions; using RISC-V across IP blocks creates a more uniform SoC toolchain and developer experience.
KEY QUOTES

In his words:

Four extended quotes from SiFive's Krste Asanovic that capture the company's strategy, technology, and market impact.

New product release: Second-gen Intelligence and the new tiny cores

So first thing to say, this is the second generation of what we call our
Intelligence line

SSCI, memory hierarchy, and AI-centric instructions

Of course one of the key things is a new, what we call SSCI, SiFive Scaler Co-Processor Interface. We already had a vector co-processor interface that allowed people to connect their accelerator directly to the vector register file. So very high data throughput, but folks also wanted a scaler co-processor interface that allows scaler register values to be communicated along with custom instructions to the accelerator for control functions. So this SSCI feature is now available across the family.
We've also made a bunch of improvements to the memory system, which is very critical for AI applications. So we've made the configurations, the multi-core configurations more efficient in terms of how the memory hierarchy is organized. And we've also added even deeper latency tolerance, so we can handle full bandwidth out to memory that may be a hundred or 200 more cycles away from the processor. And finally, we've added a lot of new instructions to help accelerate key pieces of AI algorithms. One example is, we've added a fully pipeline exponential functional unit that can provide very high throughput for exponential functions, which are a key component of many of the new activation functions being used in AI applications.
ABOUT THE AUTHOR
James Maguire
Executive Director
An award-winning journalist, James has held top editorial roles in several leading technology publications, covering enterprise trends in cloud computing, AI, data analytics, cybersecurity and more. He regularly communicates with industry analysts and experts and has interviewed hundreds of technology executives.