In this TechVoices conversation, Krste Asanovic, Co-Founder and Chief Architect at SiFive, outlines the company’s newest AI-focused RISC-V designs, including ultra-small X160 and X180 cores for pairing with custom accelerators, a new scalar co-processor interface (SSCI), deeper memory-latency tolerance, and specialized instructions for modern activation functions.
Asanovic contrasts SiFive’s IP-licensing model with proprietary approaches, details how open standards reduce fragmentation, and highlights real-world deployments of SiFive IP for processor cores—from electric vehicle ADAS to NASA’s spaceflight computers—while forecasting a continued shift toward general-purpose architectures.




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